By Bramhananda Marathe,Sandhya Nerale
The objective of this e-book is to supply perception and instinct into the analog and analog-mixed sign procedure verification. it's also a trip the writer of this e-book has been via with the intention to take on useful layout and verification demanding situations with country of artwork analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is especially varied than analog layout and verification. frequently, the analog block point verification is played through the analog designers, and electronic layout verification is played by way of electronic layout verification engineer. loss of pass area ability set makes it difficult to accomplish verification at mixed-signal point. for this reason, both analog clothier engineer should still research complicated electronic verification thoughts or electronic layout verification engineer embody analog verification to develop into analog-mixed sign verification engineer. This booklet is written preserving this new development in brain, therefore it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification heritage in brain, the e-book has first five chapters serious about the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 specializes in the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low strength verification strategies.
Chapter 1: creation to Analog combined sign Verification
This bankruptcy discusses in regards to the evolution of the verification methodologies, heritage of analog-mixed sign designs, functions, and destiny tendencies.
Chapter 2: Analog layout basics
The goal of this bankruptcy is to offer an outline of the analog layout basics for electronic layout historical past engineers. significant concentration is given on analog habit, layout standards and their idea instead of layout themselves, reminiscent of voltage/current reference, the various simple key analog layout homes corresponding to achieve, band width, fundamentals of jitter, eye diagram, and so on.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout movement, combinational and sequential common sense layout basics, layout for testability, ideas of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy makes a speciality of analog functionality verification and practical verification below the context of combined sign layout hierarchical verification instead of the element functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are advanced over the interval which are predicated on predictable caliber and verification potency. The bankruptcy includes the sections at the assurance pushed verification (CDV) method, statement dependent verification (ABV) technique, and review of the CDV utilizing Open Verification technique (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses in regards to the AMS verification stages, selecting the best abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains in regards to the functions of analog behavioral types, modeling method, easy examples of varied analog behavioral modeling types, choice of accuracy point of the versions in line with the verification plan, version verification, and signoff.
Chapter eight: Low strength Verification
The objective of this bankruptcy is to provide an explanation for the low energy layout verification demanding situations, key low energy layout components, low energy layout ideas, low energy layout and verification cycle, testplanning for low energy layout verification, energy conscious electronic, and AMS simulations
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